|Research Fields||Integrated circuits, computer hardware, dependable system|
|Academic Society Membership||IEICE, IEEE|
The number of devices connected to the Internet and the amount of data they generate has exploded in recent years and this growth is expected to continue for the foreseeable future. A driving factor behind this is the rapid uptake of mobile devices. Furthermore, the growth curve of Internet-connected devices is expected to get much steeper in the near future as more and more “smart” objects are being equipped with embedded sensors, actuators and communications capability, connecting to each other to create the Internet of Things.
The canonical architecture uses a content-addressable memory (CAM) to do a single clock cycle lookup. While fast, CAMs are very large and power-hungry, especially ternary content-addressable memories (TCAMs) that can match IP address containing wildcards. The reason for the large silicon area and high power consumption is due to the architecture of TCAMs: input data are compared with every stored entry at once. This brute-force technique is neither area nor power efficient. Although there has been much research on lowering the power consumption of TCAMs, further power reductions depend on more radical architectural innovations.
In this project, we propose to implement a low-power large-scale IP lookup engine based on sparse clustered networks (SCNs). Unlike TCAMs that store IP addresses themselves, the proposed hardware stores the associations between IP addresses and output rules, increasing memory efficiency. The output rule can be determined by simple, distributed hardware using a few associations read from SRAMs, which greatly reduces the search power dissipation compared to that of a TCAM using a brute-force search. Simulation results show the potential for an order-of-magnitude reduction in energy compared to highly-optimized TCAM designs.